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| (R) ISL6232 Data Sheet April 18, 2005 FN9116.0 High Efficiency System Power Supply Controller for Notebook Computers The ISL6232 is a high efficiency, quad output controller optimized for converting battery, wall adapter or network DC input voltage into system supply voltages required for portable applications. The ISL6232 includes two PWM controllers generating 0.8V to 5.5V, or fixed 5V and 3.3V outputs. It also features 5V and 3.3V always linear regulators with up to 100mA output current. ISL6232 uses constant frequency current mode PWM control with out of phase operation for reducing the input ripple current and the ESR requirement of the input capacitors. Over 95% efficiency is achieved through synchronous rectification and dual PWM/Skip mode architecture. High light load efficiency with skip mode extends the battery life in system standby or shutdown mode. The 5V and 3.3V always linear regulators take their inputs from battery or ac adapter; and, to further improve efficiency, their outputs are switched to the 5V or 3.3V outputs from switching regulators when 5V or 3.3V is available. Ultrasonic pulse skipping mode maintains switching frequency above 25kHz to eliminate the audio noise for high light load efficiency, and fixed frequency PWM operation mode reduces the RF interference in sensitive applications. External loop compensation is used to optimize the transient response with optimized external components. An accurate current sensing resistor in series with an output inductor, or DC resistance of the inductor is used to sense the output current of the current ramp signal, and overcurrent protection. A peak current detecting scheme is used for overcurrent protection and to prevent the inductor from saturation. The ISL6232 has internal soft-start to control the inrush current. The soft-stop feature avoids negative output voltage for undervoltage protection, overcurrent protection, and shutdown by discharging output through an internal switch, and by damping the inductor current. The ISL6232 also features overvoltage protection, power-up sequences, power good output, and thermal shutdown. It has quiescent power dissipation as low as 3.5mW. Features * Supply Voltage Range: 5.5V to 25V * 3.3V and 5V Fixed or Adjustable Outputs from 0.8V to 5.5V * 5V, 3.3V/100mA Always Linear Regulators * Out of Phase Operation Reduces the ESR Requirement of the Input Capacitors * 1.5% Output Voltage Accuracy over Temperature * Fixed 300kHz Current Mode Control Architecture * Accurate Current Sensing or DCR Current Sensing * Internal Soft-Start and Soft-Stop Output Discharge * Selectable Power-up Sequence * Selectable Forced PWM, Pulse Skipping, and Ultrasonic Pulse Skipping Mode (25kHz min) * Peak Overcurrent Limit Prevents Inductor Saturation * Overvoltage Protection, Undervoltage Shutdown * Power Good Output * Thermal shutdown * 5A Shutdown Current * Integrated Bootstrap Schottky Diodes * 3.5mW Quiescent Power Dissipation * Pb-Free Available (RoHS Compliant) Applications * Notebook, Sub-notebook, and Tablet Computers * 2-4 cell Li-Ion Battery-Powered Devices * Dual Output Supplies for DSP, Memory, Logic and Microprocessor * Telecom Systems, Network servers, and Storage Ordering Information PART NUMBER* ISL6232CAZA (Note 1) TEMP. RANGE (C) -10 to 100 PACKAGE 28 Ld QSOP (Pb-free) PKG. DWG. # M28.15 NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. *Add "-T" for Tape and Reel. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL6232 Pinout ISL6232 (QSOP) TOP VIEW OUT3 CS3 EN3 PGOOD COMP3 FB3 SHDN# SKIP# REF GND FB5 COMP5 EN5 CS5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 BOOT3 PHASE3 UGATE3 LGATE3 LDO3 PGND VIN LDO5 LGATE5 VCC UGATE5 PHASE5 BOOT5 OUT5 2 FN9116.0 April 18, 2005 ISL6232 Absolute Maximum Ratings SHDN#, VIN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +28V BOOT3, BOOT5 to GND . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +33V VCC, LDO3, LDO5, CS3, CS5, OUT3, OUT5, COMP3, COMP5, FB3, FB5, SKIP#, FREQ, PGOOD, EN3, EN5, REF to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V BOOT3 to PHASE3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V BOOT5 to PHASE5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V UGATE3 to PHASE3 . . . . . . . . . . . . . . . . . . -0.3V to (BOOT3+0.3V) UGATE5 to PHASE5 . . . . . . . . . . . . . . . . . . -0.3V to (BOOT5+0.3V) LGATE3 to GND . . . . . . . . . . . . . . . . . . . . . . -0.3V to (LDO5+0.3V) LGATE5 to PGND . . . . . . . . . . . . . . . . . . . . . -0.3V to (LDO5+0.3V) PHASE3 to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-1V to 28V PHASE5 to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to 28V PGND to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Thermal Information Thermal Resistance JA (C/W) QSOP Package (Note 1) . . . . . . . . . . . . . . . . . . . . . 77 Junction Temperature Range. . . . . . . . . . . . . . . . . .-55C to +150C Operating Temperature Range . . . . . . . . . . . . . . . -10C to +100C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Lead Temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . . +300C CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications PARAMETER SMPS CONTROLLER VIN Voltage Range 3.3V Fixed Output Voltage 5.0V Fixed Output Voltage FB3/FB5 at Programmable Mode VIN = 12V, SHDN# = EN3 = EN5 = VCC, SKIP# = FB3 = FB5 = 0V, ILDO5 = 0mA, ILDO3 = 0mA, CREF = 0.22F, CLDO3 = CLDO5 = 4.7F, TA = -10C to +100C, unless otherwise noted. TEST CONDITIONS MIN TYP MAX UNITS (Note 3) VIN = 5.5V to 25V, FB3 = 0V, SKIP# = VCC VIN = 5.5V to 25V, FB5 = 0V, SKIP# = VCC VIN = 5.5V to 25V, SKIP# = VCC 5.5 3.250 5.023 0.788 0.1 3.300 5.100 0.800 0.2 25 3.350 5.177 0.812 0.3 5.5 0.005 -0.1 -0.5 -0.5 0.1 0.1 0.01 1 1 0.1 150 96 26 V V V V V V %/V FB3/FB5 Programmable Mode Threshold Voltage OUT3/OUT5 Voltage Range at Programmable Mode Line Regulation (Note 3) VIN = 5.5V to 25V @ OUT3 VIN = 5.5V to 25V @ OUT5 SKIP# = VCC, IOUT = 0A to 5A Load Regulation SKIP# = 0V, IOUT = 0A to 5A SKIP# = REF, IOUT = 0A to 5A OUT3/OUT5 Input Leakage Current CS3/CS5 Input Leakage Current FB3/FB5 Input Bias Current COMP3/COMP5 Trans-Conductance Positive Current Limit Threshold Pulse Skipping Current Threshold Zero Crossing Current Threshold Negative Current Limit Threshold Operating Frequency Maximum Duty Cycle OUT3/OUT5 Soft-Start Period EN = VCC LDO5 = OUT = 5.5V, EN3 = EN5 = 0V LDO5 = CS = 5.5V, EN3 = EN5 = 0V FB = 0.75V COMP = 2.5V CS-OUT CS-OUT CS-OUT CS-OUT VIN = 5.5V to 25V 0.8 % A A A S mV mV mV mV 50 64 3 100 80 13 6 -20 255 94 1.0 300 345 kHz % 1.2 1.4 ms 3 FN9116.0 April 18, 2005 ISL6232 Electrical Specifications PARAMETER UGATE/LGATE Gate Driver Sink Current UGATE/LGATE Gate Driver Source Current UGATE Gate Driver Pull-Up Resistance UGATE Gate Driver Pull-Down Resistance LGATE Gate Driver Pull-Up Resistance LGATE Gate Driver Pull-Down Resistance OUT3/OUT5 On-Resistance at Discharge Mode OUT3/OUT5 Low-Side Switch Turn-On Threshold at Discharge Mode LINEAR REGULATOR AND REFERENCE VIN Shutdown Current VIN Standby Current VIN Operating Supply Current LDO5 Output Voltage LDO5 Maximum Output Current LDO5 Current Limit LDO5 Undervoltage Lockout Threshold VIN = 5.5V to 25V, SHDN# = 0V VIN = 5.5V to 25V, EN3 = EN5 = 0 LDO5 switched to OUT5, 5V SMPS enabled and LDO3 switched to OUT3, 3.3V SMPS enabled. VIN = 5.5V to 25V, EN3 = EN5 = 0, ILDO5 = 0 to 100mA VIN = 5.5V to 25V, EN3 = EN5 = 0 LDO5 pulled to GND Rising Edge Falling Edge LDO5 Switch-Over Threshold LDO5 Switch-Over Resistance LDO3 Output Voltage LDO3 Maximum Output Current LDO3 Current Limit LDO3 Switch-Over Threshold OUT5 to LDO5 VIN = 5.5V to 25V, EN3 = EN5 = 0, ILDO3 = 0 to 100mA VIN = 5.5V to 25V, EN3 = EN5 = 0 LDO3 pulled to GND Rising Edge Falling Edge LDO3 Switch-Over Resistance Quiescent Power Consumption REF Output Voltage REF Load Regulation FAULT DETECTION Output Overvoltage Trip Threshold Output Overvoltage Fault Propagation Delay Output Undervoltage Trip Threshold Output Undervoltage Latch Blanking Time PGOOD Trip Threshold OUT is above the target voltage at no load Rising FB = 1.0V OUT is below the target voltage at no load FB = 0.5V Rising (After soft-start cycle complete) Falling PGOOD Propagation Delay PGOOD Low Level Voltage FB = 0.8V ISINK = 5mA 83 70 15 75 20 91 88 10 0.1 20 0.2 109 113 117 1 78 25 97 % s % ms % % s V OUT3 to LDO3 VIN = 5.5V to 25V, FB3 = FB5 = SKIP# = 0V, Both SMPSs are enabled No Load 0A FN9116.0 April 18, 2005 ISL6232 Electrical Specifications PARAMETER PGOOD Leakage Current Thermal Shutdown Threshold Hysteresis INPUTS EN3/EN5 Input Voltage Low Delay start threshold voltage High SKIP# Input Voltage Low Ultrasonic skip mode threshold voltage High SHDN# Input Voltage Low High Input Leakage Current NOTES: 2. Specifications to -10C are guaranteed by design and not production tested. 3. Guaranteed by design. EN3/EN5/SKIP#/SHDN# 2.4 -1 1 REF0.05 2.4 0.7 V A REF REF0.05 2.4 0.8 REF+ 0.2 V REF 0.8 REF+ 0.2 V Forced to VCC VIN = 12V, SHDN# = EN3 = EN5 = VCC, SKIP# = FB3 = FB5 = 0V, ILDO5 = 0mA, ILDO3 = 0mA, CREF = 0.22F, CLDO3 = CLDO5 = 4.7F, TA = -10C to +100C, unless otherwise noted. (Continued) TEST CONDITIONS MIN -1 150 25 TYP MAX 1 UNITS A C 5 FN9116.0 April 18, 2005 ISL6232 Typical Operating Performance 100 90 EFFICIENCY (%) EFFICIENCY (%) 80 7V-SKIP 70 60 50 40 30 20 10 0 0.001 0.010 0.100 1.000 3.3V OUTPUT LOAD (A) 10.000 12V-SKIP 25V-SKIP 7V-PWM 12V-PWM 25V-PWM Circuit in Figure 29, no load on LDO5, LDO3, OUT3 OUT5, and REF, VIN = 12V, EN3 = EN5 = VCC, SHDN# = VIN, TA = 25C, unless otherwise noted. 100 90 80 70 60 50 40 30 20 10 0 0.001 0.010 0.100 1.000 3.3V OUTPUT LOAD (A) 10.000 7V-ULTRA SKIP 12V-ULTRA SKIP 25V-ULTRA SKIP FIGURE 1. EFFICIENCY OF 3.3V OUTOUT vs LOAD (7V, 12V, 25V-PWM, SKIP) FIGURE 2. EFFICIENCY OF 3.3V OUTPUT vs LOAD (7V, 12V, 25V-ULTRA SKIP) 350 300 FREQUENCY (kHz) 250 200 150 100 50 0 0.001 0.010 0.100 1.000 10.000 3.3V OUTPUT LOAD (A) 100.000 7V-ULTRA SKIP 7V-SKIP 7V-PWM 350 300 250 200 150 100 50 0 0.001 0.010 0.100 1.000 3.3V OUTPUT LOAD (A) 10.000 12V-ULTRA SKIP 12V-SKIP 12V-PWM FREQUENCY (kHz) FIGURE 3. FREQUENCY OF 3.3V OUTPUT vs LOAD (7V-PWM, SKIP, ULTRA SKIP) FIGURE 4. FREQUENCY OF 3.3V OUTPUT vs LOAD (12V-PWM, SKIP, ULTRA SKIP) 350 300 OUTPUT VOLTAGE (V) FREQUENCY (kHz) 250 200 150 100 50 0 0.001 0.010 0.100 1.000 3.3V OUTPUT LOAD (A) 10.000 25V-ULTRA SKIP 25V-SKIP 25V-PWM 3.34 12V-ULTRA SKIP 3.32 3.30 3.28 3.26 3.24 3.22 3.20 0.001 12V-SKIP 12V-PWM 0.010 0.100 1.000 3.3V OUTPUT LOAD (A) 10.000 FIGURE 5. FREQUENCY OF 3.3V OUTPUT vs LOAD (25V-PWM, SKIP, ULTRA SKIP) FIGURE 6. OUTPUT VOLTAGE REGULATION OF 3.3V vs LOAD (12V-PWM, SKIP, ULTRA SKIP) 6 FN9116.0 April 18, 2005 ISL6232 Typical Operating Performance 100 90 OUTPUT RIPPLE (mV) 80 70 60 50 40 30 20 10 0 0.001 0.010 0.100 1.000 3.3V OUTPUT LOAD (A) 10.000 12V-PWM 12V-ULTRA SKIP 12V-SKIP EFFICIENCY (%) Circuit in Figure 29, no load on LDO5, LDO3, OUT3 OUT5, and REF, VIN = 12V, EN3 = EN5 = VCC, SHDN# = VIN, TA = 25C, unless otherwise noted. (Continued) 100 90 80 7V-SKIP 12V-SKIP 70 25V-SKIP 60 50 40 30 20 10 0 0.001 0.010 0.100 1.000 5V OUTPUT LOAD (A) 10.000 7V-PWM 12V-PWM 25V-PWM FIGURE 7. OUTPUT RIPPLE OF 3.3V vs LOAD (12V-PWM, SKIP, ULTRA SKIP) FIGURE 8. EFFICIENCY OF 5V OUTPUT vs LOAD (7V, 12V, 25V-PWM, SKIP) 100 90 80 FREQUENCY (kHz) EFFICIENCY (%) 70 60 50 40 30 20 10 0 0.001 0.010 0.100 1.000 5V OUTPUT LOAD (A) 10.000 7V-Ultra SKIP 12V-Ultra SKIP 25V-Ultra SKIP 350 300 250 200 150 100 50 0 0.001 7V-ULTRA SKIP 7V-SKIP 7V-PWM 0.010 0.100 1.000 5V OUTPUT LOAD (A) 10.000 FIGURE 9. EFFICIENCY OF 5V OUTPUT vs LOAD (7V, 12V, 25V-UPTRA SKIP) FIGURE 10. FREQUENCY OF 5V OUTPUT vs LOAD (7V-PWM, SKIP, ULTRA SKIP) 350 300 FREQUENCY (kHz) 250 200 150 100 50 0 0.001 12V-ULTRA SKIP 12V-SKIP 12V-PWM FREQUENCY (kHz) 350 300 250 200 150 100 50 0 0.001 25V-ULTRA SKIP 25V-SKIP 25V-PWM 0.010 0.100 1.000 5V OUTPUT LOAD (A) 10.000 0.010 0.100 1.000 5V OUTPUT LOAD (A) 10.000 FIGURE 11. FREQUENCY OF 5V OUTPUT vs LOAD (12V-PWM, SKIP, ULTRA SKIP) FIGURE 12. FREQUENCY OF 5V OUTPUT vs LOAD (25V-PWM, SKIP, ULTRA SKIP) 7 FN9116.0 April 18, 2005 ISL6232 Typical Operating Performance 5.20 Circuit in Figure 29, no load on LDO5, LDO3, OUT3 OUT5, and REF, VIN = 12V, EN3 = EN5 = VCC, SHDN# = VIN, TA = 25C, unless otherwise noted. (Continued) 60 50 40 30 20 10 12V-PWM 12V-ULTRA SKIP 12V-SKIP OUTPUT VOLTAGE (V) 5.15 5.10 12V-SKIP 5.05 12V-ULTRA SKIP OUTPUT RIPPLE (mV) 12V-PWM 5.00 0.001 0.010 0.100 5V OUTPUT LOAD (A) 1.000 10.000 0 0.001 0.010 0.100 5V OUTPUT LOAD (A) 1.000 10.000 FIGURE 13. OUTPUT VOLTAGE REGULATION OF 5V vs LOAD (12V-PWM, SKIP, ULTRA SKIP) FIGURE 14. OUTPUT RIPPLE OF 5V vs LOAD (12V-PWM, SKIP, ULTRA SKIP) 50 BATTERY CURRENT (mA) BATTERY CURRENT (A) 6 8 10 12 14 16 18 20 22 24 26 45 40 35 30 25 20 700 600 500 400 300 200 100 6 8 10 12 14 16 18 20 22 24 26 INPUT VOLTAGE (V) INPUT VOLTAGE (V) FIGURE 15. PWM NO-LOAD BATTERY CURRENT vs INPUT VOLTAGE FIGURE 16. IDLE NO-LOAD BATTERY CURRENT vs INPUT VOLTAGE 160 158 BATTERY CURRENT (A) 156 154 152 150 148 146 144 142 140 6 8 10 12 14 16 18 20 22 24 26 BATTERY CURRENT (A) 5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 6 8 10 12 14 16 18 20 22 24 26 INPUT VOLTAGE (V) INPUT VOLTAGE (V) FIGURE 17. STANDBY INPUT CURRENT vs INPUT VOLTAGE FIGURE 18. SHUTDOWN INPUT CURRENT vs INPUT VOLTAGE 8 FN9116.0 April 18, 2005 ISL6232 Typical Operating Performance 3.5 LDO3 OUTPUT VOLTAGE (V) 3.4 3.3 3.2 3.1 3 2.9 EN3=VCC EN3=0 LDO5 OUTPUT VOLTAGE (V) Circuit in Figure 29, no load on LDO5, LDO3, OUT3 OUT5, and REF, VIN = 12V, EN3 = EN5 = VCC, SHDN# = VIN, TA = 25C, unless otherwise noted. (Continued) 5.2 5.15 5.1 5.05 5 4.95 4.9 4.85 4.8 0 10 20 30 40 50 60 70 80 90 100 EN5=0 EN5=VCC 0 10 20 30 40 50 60 70 80 90 100 LDO3 OUTPUT CURRENT (mA) LDO3 OUTPUT CURRENT (mA) FIGURE 19. LDO3 REGULATION OUTPUT VOLTAGE vs OUTPUT CURRENT FIGURE 20. LDO5 REGULATION OUTPUT VOLTAGE vs OUTPUT CURRENT 2 1.99 1.98 1.97 LDO3 1.96 1.95 -10 (1V/div) VREF (V) VIN (5V/div) LDO5 (2V/div) REF 0 10 20 30 40 50 60 IREF (A) 70 80 90 100 (1V/div) FIGURE 21. REFERENCE VOLTAGE vs OUTPUT CURRENT FIGURE 22. REF, LDO3, AND LDO5 POWER UP EN (2V/div) EN5 (2V/div) VOUT3 (2V/div) VOUT3 (2V/div) VOUT5 (2V/div) VOUT5 (2V/div) FIGURE 23. DELAYED START WAVEFORMS (EN5=REF) FIGURE 24. DELAYED START WAVEFORMS (EN3=REF) 9 FN9116.0 April 18, 2005 ISL6232 Typical Operating Performance Circuit in Figure 29, no load on LDO5, LDO3, OUT3 OUT5, and REF, VIN = 12V, EN3 = EN5 = VCC, SHDN# = VIN, TA = 25C, unless otherwise noted. (Continued) VOUT5 (100mV/div) IL3 (2A/div) IL5 (5A/div) IL3 (2A/div) VOUT3 VOUT5 (2V/div) (5V/div) LGATE3 (5V/div) FIGURE 25. SOFT-START WAVEFORMS FIGURE 26. 5V PWM-MODE LOAD TRANSIENT RESPONSE VOUT3 (100mV/div) IL3 LGATE3 (2A/div) (5V/div) FIGURE 27. 3.3V PWM-MODE LOAD TRANSIENT RESPONSE Functional Pin Descriptions BOOT3 It powers the upper MOSFET driver for OUT3. Connect a 0.1F ceramic capacitor to PHASE3. LDO3 3.3V internal LDO output. It can provide a total of 100mA. If OUT3 is greater than the LDO3 switch-over threshold, the LDO3 regulator shuts down and LDO3 pin connects to OUT3 through a 2.5 switch. Bypass a 4.7F ceramic capacitor to ground. BOOT5 It powers the upper MOSFET driver for OUT5. Connect a 0.1F ceramic capacitor to PHASE5. FB3, FB5 Output feedback inputs for OUT3 and OUT5. Connect to ground for fixed 3.3V and 5V outputs. Connect to output through a voltage divider for adjustable outputs. UGATE3 High side N-MOSFET gate drive output for OUT3. Swing between PHASE3 and BOOT3. CS3, CS5 Inductor current sensing positive inputs for OUT3 and OUT5. The current sensing signal is compared with the 80mV internal set threshold to perform overcurrent protection. It has negative 20mV current limit for ultrasonic skipping mode operation. It is also used as current ramp for current mode control. UGATE5 High side N-MOSFET gate drive output for OUT5. Swing between PHASE5 and BOOT5. LGATE3, LGATE5 Low-side N-MOSFET gate drive outputs for OUT3 and OUT5, respectively. Swing between 0V and LDO5. 10 FN9116.0 April 18, 2005 ISL6232 PGOOD Open drain output. Active high after soft-start cycle delay when both outputs are above 90% of the regulated voltage; Pull low immediately when either output is below 90% of the regulated output. PHASE3, PHASE5 Phase connection pins for OUT3 and OUT5, respectively. Connect to joint points of the high side MOSFET source, output inductor, and low side MOSFET drain. OUT5 Connect to the 5V output. It is used to sense the output voltage and connect to the negative terminal of the sensing resistor. If OUT5 is greater than the LDO5 switch-over threshold, the LDO5 internal linear regulator shuts down and LDO5 connects to OUT5 through a 2 switch. GND Analog ground. VIN This pin is the input of the internal 5V and 3.3V LDO regulators. Connect VIN to the battery or AC adapter output. LDO5 5V internal LDO output. LDO5 is the gate driver supply for the external MOSFETs. It can provide a total of 100mA, including MOSFET gate drive requirements and external loads. If OUT5 is greater than the LDO5 switch-over threshold, the LDO5 regulator shuts down and LDO5 pin connects to OUT5 through a 2 switch. Bypass a 4.7F ceramic capacitor to ground. OUT3 Connect to the 3.3V output. It is used to sense the output voltage and connected to the negative terminal of the sensing resistor. If OUT3 is greater than the LDO3 switchover threshold, the LDO3 internal linear regulator shuts down and LDO3 connects to OUT3 through a 2.5 switch. PGND Power ground. VCC VCC is derived from LDO5. This pin is used to power the internal analog integrated circuit only. The only connection to this pin is a 0.1F ceramic capacitor to ground. SHDN# Shut down control input. Connect to ground, for shuting down all internal circuitry. Connect to VIN for automatic start up. EN3 3.3V output enable input. Connect to high for enabling 3.3V output. Connect to low for disabling 3.3V output. When it is connected to REF, the 3.3V output starts after 5V output reaches regulation. Drive EN3 below the clear fault level to reset the fault latches. SKIP# Mode selection input. Connect to ground for pulse skip operation. Connect to VCC for forced PWM operation. Connect to REF for ultrasonic pulse skipping operation. For debugging purposes, SKIP# can be pulled 1V above VCC to disable the latch-off features of overcurrent, undervoltage, and overvoltage protections. EN5 5V output enable input. Connect to high for enabling 5V output. Connect to low for disabling to 5V output. When it is connected to REF, the 5V output starts after 3.3V output reaches regulation. Drive EN5 below the clear fault level to reset the fault latches. REF Reference output. Bypass a 0.22F ceramic capacitor to ground. REF can source up to 100uA for external loads. COMP3, COMP5 External loop compensation for OUT3 and OUT5, respectively. Connect a resistor in series with a capacitor to ground. 11 FN9116.0 April 18, 2005 ISL6232 Typical Operating Performance Typical Application Circuits The typical application circuits shown in Figure 28 and Figure 29 generate 5V/5A and 3.3V/5A for system power supplies in a notebook computer. VIN: 5.5V to 25V C13 0.1F 5V ALWAYS ON VIN C10 10F Q3 IRF7807V R2: 8m,1% L2: 4.7F ,1% Q4 IRF7811AV VCC ISL6232 BOOT3 UGATE3 PHASE3 LGATE3 CS3 OUT3 GND C3 R3 270pF 390k FB3 COMP3 SKIP# BOOT5 UGATE5 PHASE5 LGATE5 PGND CS5 OUT5 FB5 COMP5 REF PGOOD VCC ON OFF EN3 EN5 SHDN# LDO3 VCC 3.3V ALWAYS ON C12 4.7 4.7F R4 R 100k 100k R5 C5 390k 270pF C1 10 10F Q1 IRF7807V L1: 6.8 H LDO5 C6 4.7F 4.7 OUT3 3.3V/5A C9 0.1F C4 0.1F 0.1 R1: 8m,1% OUT5 5V/5A C11 220 220F 12mW 4.0V Q2 IRF7811AV C2 180F 12mW 6.3V VCC C7 0.22F 0.22 FIGURE 28. ISL6232 TYPICAL APPLICATION CIRCUIT WITH ACCURATE CURRENT SENSING 12 FN9116.0 April 18, 2005 ISL6232 VIN: 5.5V to 22V C13 0.1F 5V ALWAYS ON VIN VCC ISL6232 C10 10F 10 Q3 IRF7807V OUT3 3.3V/5A Rdc218m L2: 4.7yH L2:4.7H Rdc2:12m C15: 0.47F R9: 1.0k Q4 IRF7811AV R4: 2.0k LGATE3 LGATE5 PGND CS3 CS5 OUT3 OUT5 GND FB5 C3 R3 270pF 300k FB3 COMP5 COMP3 REF SKIP# PGOOD REF ON SHDN# OFF LDO3 EN3 EN5 C7 0.22 0.22F R6 100k R5 C5 390k 270pF VCC R8: 3k C9 0.1F BOOT3 UGATE3 PHASE3 BOOT5 UGATE5 PHASE5 C4 0.1F 0. LDO5 C14 1F 1 C1 10 10F Q1 IRF7807V L1:6.8H Rdc1:12m L1:6.8yH Rdc1:22m R7: R7:1.5k Q2 IRF7811AV C8: 0.47F C6 4.7 4.7F OUT5 5V/5A C2 180F 12m 6.3V C11 220 220F 12m 4.0V VCC 3.3V ALWAYS ON C12 4.7 4.7F FIGURE 29. ISL6232 TYPICAL APPLICATION CIRCUIT WITH DCR CURRENT SENSING Theory of Operation The ISL6232 is a high-efficiency quad output controller optimized for converting battery, wall adapter, or network DC input voltage into system supply voltages required for portable applications where high efficiency and low quiescent supply current are required. The ISL6232 includes two PWM controllers that are fixed at 5V and 3.3V respectively, or they can be programmed from 0.8V to 5.5V. Figure 30 shows its functional block diagram. ISL6232 uses a constant-frequency, 300kHz, peak current-mode PWM control scheme with 180o out-of-phase operation for reducing the input ripple current and also ESR requirement of the input capacitors. Light-load efficiency is improved by the variable-frequency pulse-skipping operation that reduces switching losses and gate-charge losses. In order to eliminate the audio noise at extremely light load condition, the ultrasonic pulse skipping mode is selectable by tying SKIP# pin to REF so that a minimum 25kHz switching frequency can be maintained. Each switching-mode step-down circuit includes two external N-MOSFETs and an LC output filter. The output voltage is the average AC voltage at PHASE node, which is regulated by changing the duty cycle of the external NMOSFETs. The gate-drive signal to the high side MOSFET must exceed VIN voltage and is provided by a 0.1F boost capacitor, which is connected between BOOT and PHASE. 13 FN9116.0 April 18, 2005 ISL6232 VCC LDO5 BOOT5 BOOT3 UGATE3 UGATE5 PHASE5 PHASE3 LGATE5 COMP5 5V SYNCH PWM BUCK CONTROLLER 3.3V SYNCH PWM BUCK CONTROLLER LGATE3 COMP3 CS5 FB5 CLK5 ENA5 DECODER 6pF PGOOD5 CLK3 ENA3 DECODER PGOOD3 6pF CS3 FB3 OUT5 OUT3 4.5V + 3.0V + + LDO5 5V LDO VIN 3.3V LDO LDO3 PGOOD OSC SHDN# EN3 EN5 SHUTDOWN STANDBY POWER-UP SQUENCE REF REF FIGURE 30. FUNCTIONAL DIAGRAM Each buck controller includes a feedback resistor divider network, a multiplexer for programmable mode, a transconductance error amplifier, a PWM comparator, high-side gate and low-side gate drivers, and control logic circuit. Figure 31 shows the synchronous buck PWM controller block diagram. The external loop compensator is used to optimize the transient response with optimized external components. An accurate current sensing resistor in series with output inductor or the DC resistance of the inductor is used to sense the output current for current ramp signal and overcurrent protection. Moreover, it contains fault-protection circuitry that can monitor the undervoltage and overvoltage conditions of the OUT3 and OUT5 buck controller output voltages. A power-on sequence is implemented to control the power-up timing of OUT3 and OUT5. The power good signal, PGOOD, is toggled to logic high once both OUT3 and OUT5 reach 90% of the regulation points and soft start period is finished. The ISL6232 also includes 5V and 3.3V linear regulators, 2V reference, and automatic switch-over circuits. All the blocks inside ISL6232 are not directly powered by VIN voltage. Instead, the VIN voltage is stepped down to 5V by the 5V LDO5 regulator to supply both internal circuitry and the gate 14 FN9116.0 April 18, 2005 ISL6232 COMP SKIP# BOOT + + 0.8V EAMP + COMP CLK Soft Start Slope Comp DC OFFSET UV + 0.2V + OCP OV CS OUT PWM/SKIP LOGIC CONTROLLER UGATE PHASE LDO5 LGATE + FB + + CSA x16 y y20 1.0V OUT + SKIP + PGOOD 0.72V + Zero Cross OV + 0.9V 0.1V NCSA x8 + + 0.06V 0.2V UV 20ms Blanking FIGURE 31. SYNCHRONOUS BUCK PWM CONTROLLER BLOCK DIAGRAM drivers. The low side drivers are directly powered from LDO5 and the high side drivers are indirectly powered from LDO5 through the internal Schottky diode and external bootstrap capacitor. Only after soft-start is finished and when OUT5 is above 4.75V, an automatic switch-over circuit turns off the internal LDO5 regulator and powers the device from OUT5. This prevents the LDO5 and LDO3 from a voltage dip during the switch-over. It switches back to LDO5 when OUT5 is disabled for EN5 = 0. Similary, only after soft-start is finished and when OUT3 is above 3.0V, it turns off the 3.3V LDO3 regulator and powers the device from OUT3. It switches back to LDO3 just before OUT3 is disabled. ISL6232 has internal soft-start to control the inrush current. This soft-stop feature avoids negative output voltage for undervoltage protection and overcurrent protection so that the part can be shut down by first discharging OUT3 or OUT5 through an internal 20 switch and damping the 15 + 0.6V NOCP inductor current. Finally, thermal shutdown is included in ISL6232 to protect the part from over-heating. PWM Controller The two-buck controllers are nearly identical. The only difference is the fixed output voltage, 3.3V versus 5V. Both buck controllers use a peak current-mode PWM control scheme. For peak current mode control, the system can be unstable when the duty cycle is higher than 0.5. A slope compensation signal is used to stabilize the system. A PWM comparator compares the integrated voltage feedback signal (COMP) with the sum of the amplified current-sense signal and the slope-compensation ramp. At each rising edge of the internal clock, the high side MOSFET turns on until the PWM comparator trips. During this on-time, current ramps up through the inductor, sourcing current to the output and storing energy in the inductor. The current-mode feedback system regulates the peak inductor current as a function of FN9116.0 April 18, 2005 ISL6232 the output voltage error signal. To preserve loop stability, a slope-compensation ramp is summed into the main PWM comparator. During the off cycle, the external high side MOSFET turns off and the external low side MOSFET turns on. The inductor releases the stored energy as its current ramps down while still providing current to the output. The output capacitor stores the charge when the inductor current exceeds the load current and releases the charge when the inductor current is lower, smoothing the voltage across the load. During an overcurrent or short-circuit condition, it immediately turns off the high side MOSFET and turns on the low side MOSFET. This peak current limit prevents the inductor from saturation. If the overcurrent still exists at the rising edge of the next clock, the high side MOSFET will stay off and the low side MOSFET remains on to let the inductor current ramp down. When SKIP# = GND, the efficiency is automatically optimized throughout the entire load current range. Skip mode significantly improves light-load efficiency by reducing the effective frequency, which reduces switching losses. The automatic transition to skip mode is determined by the current's zero-cross comparator, which detects inductor current zero crossing and turns off the low side MOSFET. The boundary is set by the following equation: V (1 - D) OUT I OUT = -----------------------------------2Lf s When SKIP# = VCC, the controller always operates in forced PWM mode for the lowest noise and zero-cross detection is bypassed. The inductor current becomes negative at light load condition because the PWM loop tries to maintain a duty cycle set by VOUT/VIN, leading to poor efficiency at light loads. During forced PWM operation, each clock rising edge sets the main PWM latch that turns on the high side switch for a period determined by the duty cycle. As the high side MOSFET turns off, the synchronous rectifier latch sets and the low side MOSFET turns on. The low side MOSFET stays on until the beginning of the next clock cycle. Table 1 shows the operation mode. TABLE 1. OPERATION MODE TABLE SKIP# GND MODE Skip LOAD CONDITION Light DESCRIPTION Pulse skipping, DCM. Turn off UGATE when the inductor current reaches the skip current threshold. Constant frequency PWM Pulse skipping, DCM. Turn on LGATE if there is no switching after 30us. Turn it off once it reaches negative current limit or PWM comparator's output has toggled to high before the next clock cycle. Constant frequency PWM Constant frequency PWM Constant frequency PWM GND REF PWM Ultrasonic Skip Heavy Light (EQ. 1) where D = duty cycle, fs = switching frequency, L = inductor value, IOUT = output loading current, VOUT = output voltage. The PWM controller keeps the peak inductor current about 15% of the overcurrent limit in an active cycle, thus allowing subsequent cycles to be skipped as long as the COMP pin voltage is low enough. The switching waveform at light load behaves noisy and is asynchronous due to pulse skipping. Skip mode transits smoothly to fixed-frequency PWM operation as load current increases. When SKIP# = REF, the ultrasonic mode is enabled so that the minimum switching frequency can be maintained higher than 25kHz. This ultrasonic pulse-skipping mode eliminates the audio noise that can occur in skip mode at very light load condition. Ultrasonic pulse skipping occurs if no switching has taken place within the last 30s. The low side MOSFET turns on to induce a negative inductor current. Then, the high side MOSFET turns on when the inductor current reaches the negative current limit, or when the PWM comparator output has toggled to high before the next clock cycle. The negative current limit is determined by the following equation: I NLIM V NLIM = ------------------R CS REF VCC VCC PWM PWM PWM Heavy Light Heavy UGATE and LGATE Drivers A 0.1F capacitor connected between BOOT and PHASE, as well as the internal Schottky diode connected from LDO5 to BOOT, generate the gate drive for the high side MOSFET. When the low side MOSFET turns on, PHASE goes to PGND. LDO5 charges the bootstrap capacitor through the Schottky diode. When the low side MOSFET turns off and the high side MOSFET turns on, PHASE voltage goes to VIN. The Schottky diode prevents the capacitor from discharging into LDO5. The LGATE synchronous rectifier drivers are powered by LDO5. Both UGATE and LGATE gate drivers sink 2A peak current out of gate terminal, ensuring adequate gate drive for highcurrent applications. The internal pull-down transistors that drive LGATE low have a 1 typical on-resistance. These low on-resistance pull-down transistors can prevent LGATE from being pulled up during the fast rise time of the PHASE nodes due to capacitive coupling from the drain to the gate of the low side MOSFETs. In the case of high-current applications, some combinations of both high side and low side MOSFETs can still cause sufficient gate-drain coupling, which leads to shoot-through currents and poor efficiency. To get around (EQ. 2) where VNLIM is the negative current limit threshold and RCS is current sense resistance. 16 FN9116.0 April 18, 2005 ISL6232 this situation, a small resistor (a few ohms) in series with the BOOT pin can be added to increase the turn-on time of the high side MOSFETs at the cost of efficiency. Dead-time control circuitry is also implemented to monitor the UGATE and LGATE voltages so that one of the external MOSFETs can be prevented from turning on before the other one completely turns off. This method can allow operation without shoot-through with a wide selection range of external MOSFETs, minimizing delays and maintaining efficiency. To achieve this, the trace from UGATE and LGATE to the MOSFET gates must be low resistance and low inductance. Otherwise, the control circuitry will regard the MOSFET gate as in the off-state when there is still some charge left on the gate. CURRENT SENSE INPUTS, CS AND OUT An internal current-sense amplifier produces a current signal proportional to the voltage generated by the sense resistance and the inductor current (RCS*IL). The amplified current-sense signal and the internal slope-compensation signal sum together at the comparator inverting input. The PWM comparator turns off the high side MOSFET when this summed voltage exceeds the COMP voltage of the error amplifier. The ISL6232 has a positive current limit threshold of 80mV with a 20% tolerance. Whenever the voltage difference between CS and OUT exceeds 80mV, the high side MOSFET turns off and the low side MOSFET turns on. This lowers the duty cycle and causes the output voltage to drop until the current limit is no longer exceeded. The external low-value sense resistor, RCS, should be picked for 65mV/IPEAK, where IPEAK is the required peak inductor current to support the full load current. Also, the other components must be chosen to sustain continuous current of 95mV/RCS. It is useful to wire the current-sense inputs with a twisted pair, which can reduce the possible noise picked up at CS and OUT as well as avoid unstable switching. A negative current limit threshold, typical of 20mV, is implemented to prevent excessive reverse inductor currents when OUT dumps charges. This negative current limit is used to determine when the low side MOSFET should turn off at ultrasonic pulse skipping mode. (DCM). In CCM mode, the boundary is set by the following equation, V OUT ( 1 - D ) I OUT = ---------------------------------2Lf s (EQ. 3) where D = duty cycle, fs = switching frequency, L = inductor value, IOUT = output loading current, VOUT = output voltage. However, the boundary is set by the following formula in DCM condition. V SKIP I OUT = ---------------2R CS (EQ. 4) where VSKIP is the current limit threshold at skip mode. The above two boundary values can not be completely matched due to the tolerance of the pulse skipping current limit threshold, inductance, frequency, and line input voltage. The ISL6232 is designed in such a way that it operates in a mixed mode between DCM mode CCM mode during the mode transition, which may have one longer pulse and is followed by one shorter pulse. But this does not affect the output ripple voltage. This is a normal operation and it is not the loop stability issue. The inductor current is regulated in the CCM mode to meet the load current requirement since the inductor current is fixed in the DCM mode during the mixed mode operation. POWER GOOD (PGOOD) PGOOD is kept low during soft-start. When both OUT3 and OUT5 voltages reach 90% of the regulation points, PGOOD toggles to high after the end of soft-start period. When either output turns off or is 10% below its regulation point , or a fault occurs in either output, PGOOD goes low. PGOOD is set to low during shutdown, standby, and soft-start. DISCHARGE MODE When the output is disabled by toggling EN3 or EN5 from high to low or latched off due to the undervoltage or overcurrent fault, it is discharged through an internal 20 switch from PHASE to PGND until the output drops to 0.3V. After the output drops below 0.3V, LGATE is forced to high to discharge the output to ground. LDO5, VCC, and REF are active at this mode. POWER-ON RESET, DIGITAL SOFT-START, AND UVLO When VIN rises above approximately 3.8V, power-on reset occurs. After internal reference voltages and bias currents are ready, both LDO3 and LDO5 are enabled. After LDO5 reaches undervoltage lockout (UVLO) voltage, 4.3V, the buck controller is enabled if either EN3 or EN5 is tied to VCC. Then, the internal digital soft-start circuitry begins to charge-up the output capacitor of the buck controller gradually in 44 steps within 1.2ms (typ), so that the VIN inrush current can be reduced. Each buck controller includes Mode Transition Between DCM and CCM The automatic transition to skip mode is determined by the current zero-cross comparator, which detects the inductor current's zero crossing and turns off the low side MOSFET. The threshold between pulse skipping pulse frequency modulation (PFM) and non-skipping PWM can not completely coincide with the boundary between continuous current mode (CCM) and discontinuous current mode 17 FN9116.0 April 18, 2005 ISL6232 its own internal digital soft-start circuit. In shutdown or standby mode, the soft-start output is reset to zero. Thermal Protection Thermal-overload protection limits total power dissipation in the device. When the junction temperature exceeds 150C, a thermal sensor forces most of the internal circuitry into shutdown mode, thus allowing the device to cool down. The thermal sensor turns the device on again after the junction temperature drops by 25C, causing a pulsed output during continuous overload conditions. The digital soft-start sequence begins after the thermal shutdown condition is removed. Fault Protection Undervoltage Protection When the output undervoltage is detected at below 75% (typ) of the regulation output for 20ms blanking time, it enters the discharge mode by discharging the output through the internal 20 switch connected from PHASE to PGND. When the output voltage drops below 0.3V, the external low side MOSFET is latched on to discharge the output to ground. When either output is in UVP, both outputs are latched off through soft-discharge. The latches can be reset by toggling VIN, SHDN#, or EN. Power-Up Sequence EN3 and EN5 control the power-up sequencing of buck controllers. Setting EN above 2.4V enables the outputs, and setting EN below 0.8V disables the outputs. Connecting EN3 or EN5 to REF forces the respective output off until the other output reaches 90% of the regulation point and soft-start cycle has ended. One of the buck controllers can remain on even though the other buck controller turns off. Table 2 shows the power sequence selection. TABLE 2. POWER-UP SEQUENCE TABLE SHDN# Low High High High High High High EN3 x Low Low High High High REF EN5 x Low High Low High REF High LDO3 OFF ON ON ON ON ON ON LDO5 5V BUCK OFF ON ON ON ON ON ON OFF OFF ON OFF ON ON after 3.3V up ON 3.3V BUCK OFF OFF OFF ON ON ON ON after 5V up Overvoltage Protection When either output voltage is above 113% (typ) of the regulation point, both outputs are latched off by turning on the low side MOSFET and turning off the high side MOSFET. Discharging the output capacitors through the inductor and low-side MOSFET causes negative output voltage. For loads that cannot tolerate a negative voltage, place a 1A power Schottky diode across the output to act as a reverse-polarity clamp. If the overvoltage is due to a short in the high side MOSFET, the battery fuse will be blown and isolated from the output. Overcurrent Protection The output current is continuously monitored through either an accurate sensing resistor or the DCR of the inductor. When the inductor peak current reaches the overcurrent limit threshold, it immediately turn off the high side MOSFET and turn on the low side MOSFET. This peak current limiting prevents inductor saturation. If the overcurrent or short circuit condition is detected for more than 20mS (typical), the high side MOSFET is latched off and the output is discharged through the internal 20 switch connected from PHASE to PGND. When the output voltage drops below 0.3V, the low side MOSFET is latched on to discharge the output to ground. When either output is latched off due to overcurrent, the other output is also latched off through softdischarge. SHUTDOWN MODE When SHDN# is set below 0.8V, the part is completely shut down with a 5A (typ) shutdown VIN current. When SHDN# is set above 2.4V, both LDO outputs and REF are active. This is prerequisite for enabling buck controllers. For automatic shutdown and startup, SHDN# can be tied to VIN. Table 3 is the summary of various operation modes. 18 FN9116.0 April 18, 2005 ISL6232 TABLE 3. SUMMARY FOR VARIOUS OPERATION MODES MODE Shutdown Standby CONDITION SHDN# = Low. SHDN# = High. EN3 = EN5 = Low. LDO5>UVLO EN3 or/and EN5 enabled. COMMENT All circuitry off. LDO5, LDO3, and 2V reference active. LGATE stays high. Output voltage ramps up in 1.2ms. Application Information This section describes how to select the external components including the inductor, input and output capacitors, switching MOSFETs, current sensing resistors and loop compensator design. The inductor selection has to accommodate trade-offs between cost, size and efficiency. For example, the lower the inductance, the smaller the inductor size, but ripple current is higher; this results in higher ac losses in the magnetic core and the windings, which decrease the system efficiency. On the other hand, the higher inductance results in lower ripple current and smaller output filter capacitors, but higher DCR (dc resistance of the inductor) loss and slower transient response. Practical inductor design is based on the inductor ripple current being (15-20)% of the maximum operating dc current at maximum input voltage. The required inductance can be calculated from: V IN - VOUT VOUT L = --------------------------------- ----------------VIN f s I L Soft-Start Normal Operation Discharge SHDN# = High. EN3 and All circuitry is running. EN5 enabled. Either output is still high Discharging the output in standby mode. through an internal 20 switch from PHASE to PGND. One output may still operate while the other is in discharge mode. LDO5 active. Lower side MOSFET is latched on after discharge mode terminates. LDO5 is active. Reset by toggling EN3, EN5, SHDN#, VIN POR. Low side MOSFET is forced high and high side MOSFET is forced low. Undervoltage Either output is below Protection 75% of nominal after a 20ms blanking time and output enabled. (EQ. 5) Overvoltage Either output voltage is Protection 13% higher than the nominal. where VIN is input voltage, VOUT is the output voltage, IL is the inductor ripple current and fs is the switching frequency. The practical inductor ripple current is chosen at 30% of the output current: I L = 30% I OUT For VIN = 12V, VOUT = 5V, IOUT = 5A, and fs = 300kHz, 12 - 5 5 L = ----------------- ------------------------------------- = 6.5H 0.3 x 5 12 x 300 x 10 3 LINEAR REGULATORS AND 2V REFERENCE In ISL6232, there are two internal regulators available, which are LDO5 (5V) and LDO3 (3.3V). Once LDO5 is higher than 4.3V, it provides power for buck controllers, 2V reference, and all the other blocks powered by VCC. The maximum guaranteed output current that both LDO5 and LDO3 regulators can supply is 100mA. The real maximum current drawn from the LDOs is determined by the maximum power dissipation allowed in the package. A short-circuit or overcurrent limit protection, 170mA (typ), is implemented for both LDO5 and LDO3. Bypass LDO5 and LDO3 with a 4.7F ceramic capacitor. When OUT5 is larger than the LDO5 switch-over threshold (4.78V) and after soft-start is finished, LDO5 is shorted to OUT5 through an internal 2 switch and the LDO5 regulator is disabled to reduce the power dissipation. Similarly, when OUT3 is larger than the LDO3 switch-over threshold (3.0V) and after soft-start is finished, LDO3 is shorted to OUT3 through an internal 2.5 switch and LDO3 is turned off. All the internal blocks (powered by VCC) get the power from the high-efficiency switching power supply instead of the linear regulator. The reference voltage, REF, is 2V with a 1.5% accuracy. REF provides the reference voltage, 0.8V, for buck controllers. REF is bypassed to GND with a 0.22F capacitor. (EQ. 6) Ferrite core inductors are often the best choice since they are optimized at 300kHz to 600kHz operation with low core loss. The inductor must be large enough not to saturate at the overcurrent limit IOC I OC = ---------------R CS 95mV (EQ. 7) One important factor is that the smaller the inductance, the faster the transient response. One of the parameters limiting the converters response to load transient is the time required to change the inductor current. Given a sufficiently fast control loop design, the ISL6232 can provide either approximately 5% or 95% duty cycle in response to a load transient. The response time is the time required to slew the inductor current from an initial current value to the transient current level. During this interval the difference between the inductor current and the transient current level must be supplied by the output capacitor. Minimizing the response time can minimize the output capacitance required. The response time to a transient is different for the application of load and the removal of load. 19 FN9116.0 April 18, 2005 ISL6232 The following equations give the approximate response time interval for application and removal of a step transient load: LI LI STEP STEP T --------------------------------- , T --------------------rise V - V fall V IN OUT OUT Check the current limit ILIMIT as the following equation: R8 -------------------- R xI = 65mV R 7 + R 8 dc1 LIMIT (EQ. 12) (EQ. 8) Where ISTEP is the transient load current step, Trise and Tfall are the response time to the application and the removal of load, respectively. The worst-case response time can be either at the application or removal of load. Be sure to check both of these equations at the minimum and maximum output levels for the worst-case response time. We have ILIMIT = 6.5A. Therefore, the circuit can easily deliver the fully rated 5A current. Output Capacitor Selection The output filter capacitor must have low enough equivalent series resistance (ESR) to meet output ripple and loadtransient requirements. The ISL6232 uses peak current mode control, which does not require high enough ESR to satisfy stability requirements. The output capacitance must also be high enough to absorb the inductor energy while transitioning from full-load to no-load conditions without tripping the overvoltage fault latch. In applications where the output is subject to large load transients, the output capacitor size depends on how much ESR is needed to prevent the output from dipping too low under a load transient, ignoring the sag due to finite capacitance. The ESR of the output capacitors has to meet the following equation: V DIP ESR < ---------------I STEP (EQ. 13) Determining the Overcurrent Limit The minimum current-limit threshold must be great enough to support the maximum load current when the current limit is at the minimum tolerance value. ISL6232 uses peak current detection. The peak inductor current occurs at IOUT,MAX plus half of the ripple current; therefore, I L I LIMIT > I OUTMAX + -------2 (EQ. 9) The minimum current-limit threshold voltage is 65mV. For accurate current sense-resistor with 8m, the current limit ILIMIT is 8.1A, which is higher than 5.75A, calculated from the above equation. So, the circuit can easily deliver fullrated 5A using 65mV current limit threshold. For DCR of inductor current sensing (Refer to Figure 29), if the voltage drop across the DCR of the inductor is higher than 65mV, then a resistor divider across the inductor has to be used so that the output voltage across the capacitor reaches current limit threshold (65mV minimum) at the maximum DCR. The inductor time constant has to match with the RC current sensing network for good current sensing accuracy, that is, L R R8 17 -------------- --------------------- C R dc1 R 7 + R 8 16 where VDIP is the maximum tolerable transient voltage drop or rise. In system power applications, the ESR of the output capacitors usually determines the steady-state output voltage ripple, which is practically designed below 1% of the output voltage. Thus, we have V pp ESR --------I L (EQ. 14) (EQ. 10) This requirement is not so stringent because it is used for overcurrent protection and not for the adaptive output voltage positioning applications. Besides, DCR of the inductor is also a function of the temperature. A good general rule for copper is to allow 3.9% additional resistance for each 10C of temperature rise. Since there is 1M input impedance from CS to ground, to achieve good current sensing accuracy, R7, and R8 have to meet the following inequality: V OUT ----------------------------- 2mV RX 1 + ------------------R //R 8 7 where Vpp is the peak-to-peak output voltage ripple. The actual capacitance value required relates to the physical size needed to achieve low ESR, as well as to the chemistry of the capacitor technology and loop bandwidth. Since the voltage dip or spike due to loop transient response is usually smaller than that of voltage dip or spike due to ESR during the load step transient, the capacitor is usually selected by ESR and voltage rating rather than by capacitance value. The commonly used output capacitors are POSCAP from Sanyo and SPCAP from Panasonic due to smaller size, low ESR and reasonable price. Most power supplies requires an overall voltage accuracy of 5%, including steady-state tolerance, steady-state output ripple, line regulation and step load transient tolerance. The ISL6232 has 1.5% accuracy for the band gap, 0.5% for steady-state output ripple and line regulation. This allows 3% tolerance due to the step load transient. For 5V output, the required ESR is given by 3% x 5V ESR ---------------------- = 50m 3A (EQ. 11) Where Rx is the input impedance from CS to ground. Given Rdc1 = 15m at 85C, L = 6.8H, we choose R7 = 1.5k, R8 = 3k, and C16 = 0.47F. (Assume 3A step load) (EQ. 15) 20 FN9116.0 April 18, 2005 ISL6232 Input Capacitor Selection The input capacitors must meet the input ripple current (IRMS) requirement imposed by the switching current. The ISL6232 dual switching regulators operate at the same switching frequency with out of phase. This interleaves the current pulses drawn by the two regulators and have no overlap time at normal operation. The input RMS current is much smaller when compared with both regulators operating in phase or operating at different switching frequencies. The input RMS current varies with load and the input voltage. The maximum input capacitor RMS current for a single buck regulator is given by: V OUT ( V IN - V OUT ) I rms = I OUT -------------------------------------------------------V IN The optimum efficiency occurs when the switching losses equal the conduction losses. However, it is difficult to calculate the switching losses in the high-side MOSFET since it must allow for difficult-to-quantify factors that influence the turn-on and turn-off times. These factors include the MOSFET internal gate resistance, gate charge, threshold voltage, stray inductance, and the pull-up and pulldown resistance of the gate driver. The following switching loss calculation provides a rough estimate. (EQ. 18) Q gd Q gd 1 1 -P Q1, Switching = -- V IN I LV f s ------------------------ + -- V IN I LP f s ---------------- + Q rr V IN f s I g, source 2 I g, sin k 2 (EQ. 16) when VIN = 2VOUT (D = 50%), Irms has maximum current of IOUT/2. The ESR of the input capacitor is important for determining capacitor power dissipation. All the power (I2rms x ESR) heats up the capacitor and reduces efficiency. Nontantalum chemistries (ceramic, polymer such as POSCAP, or SPCAP) are preferred due to their low ESR and resilience to power-up surge currents. Choose input capacitors that exhibit less than +10C temperature rise at the RMS input current for optimal circuit longevity. where Qgd: drain-to-gate charge, Qrr: total reverse recovery charge of the body-diode in low side MOSFET, ILV: inductor valley current, ILP:is Inductor peak current, Ig,sink and Ig,source are the peak gate-drive source/sink current of Q1. To achieve low switching losses requires low drain-to-gate charge Qgd. Generally, the lower the drain-to-gate charge, the higher the on-resistance. Therefore, there is a trade-off between the on-resistance and drain-to-gate charge. Good MOSFET selection is based on the Figure of Merit (FOM), which is the product of the total gate charge and onresistance. Usually, the smaller the value of FOM, the higher the efficiency for the same application. For the low-side MOSFET, the worst-case power dissipation occurs at minimum output voltage and maximum input voltage: V OUT 2 P Q2 = 1 - --------------- I OUT R DSON V IN (EQ. 19) MOSFET Selection The synchronous buck regulator has the input voltage from either AC adapter output or battery output. The maximum AC adapter output voltage does not exceed 24V while the maximum battery voltage does not exceed 17V for a 4 series Li-Ion battery cell battery pack. Therefore, a 30V logic MOSFET should be used. The high side MOSFET must be able to dissipate the conduction losses plus the switching losses. The input voltage of the synchronous regulator is equal to the AC adapter output voltage or battery voltage. The maximum efficiency is achieved by selecting a high side MOSFET that has the conduction losses equal to the switching losses. Ensure that the ISL6232 LGATE gate driver can supply sufficient gate current to prevent it from conduction, otherwise, cross-conduction problems may occur. Conduction is due to the injected current into the drain-togate parasitic capacitor (Miller capacitor Cgd) caused by the voltage rising rate at phase node during the moment of the high-side MOSFET turn-on. Reasonably slowing turn-on speed of the high-side MOSFET by connecting a resistor between the BOOT pin and gate drive supply source, and high sink current capability of the low-side MOSFET gate driver, helps reduce the possibility of cross-conduction. For the high-side MOSFET, the worst-case conduction losses occur at the minimum input voltage: V OUT 2 P Q1, Conduction = --------------- I OUT R DSON V IN (EQ. 17) Choose a low-side MOSFET that has the lowest possible on-resistance with a moderate-sized package, like SO-8, and one that is reasonably priced. The switching losses are not an issue for the low side MOSFET because it operates at zero-voltage-switching. Choose an Schottky diode, in parallel with the low side MOSFET Q2, with a forward voltage drop low enough to prevent the low-side MOSFET Q2 body-diode from turning on during the dead time. This also reduces the power loss in the high-side MOSFET associated with the reverse recovery of the low-side MOSFET Q2 body diode. As a general rule, select a diode with a DC current rating equal to one-third of the load current. One option is to choose a combined MOSFET with the Schottky diode in a single package. The integrated packages may work better in practice because there is less stray inductance due to short connection. This Schottky diode is optional and may be removed if efficiency loss can be tolerated. Loop Compensation Design ISL6232 uses constant frequency peak current mode control architecture to achieve fast loop transient response. An accurate current sensing resistor in series with the output 21 FN9116.0 April 18, 2005 ISL6232 inductor, or DCR of the output inductor, is used for peak current control signal and overcurrent protection. The inductor is not considered as a state variable since its peak current is constant, and the system becomes single order system. It is much easier to design a type II compensator to stabilize the loop than to implement voltage mode control. Peak current mode control has inherent input voltage feedforward function to achieve good line regulation. Figure 32 shows the small signal model of the synchronous buck regulator. ^ ^ iL ^ Power Stage Transfer Functions Transfer function F1(S) from control to output voltage is: S 1 + ---------- esr vo F 1 ( S ) = ------ = V in ------------------------------------- 2 d S S ------ + -------------- + 1 2 Q op o 1 1 o Where esr = -------------- ,Q p R o ------ , o = -------------Rc Co L C LC o (EQ. 23) Transfer function F2(S) from control to inductor current is given by: S 1 + ----- z V in Io F 2 ( S ) = ---- = -------------------- ------------------------------------- Ro + RL 2 d S S ------ + -------------- + 1 2 Q op o 1 where z = -------------- . Ro Co (EQ. 24) i in I Ld L v^ o ^ Vin 1:D ^ Vind + Rc Ro Co Ti(S) + RT ^ d Current loop gain Ti(S) is expressed as the following equation: K T i ( S ) = R T F m F 2 ( S )H e ( S ) Fm Tv (S) ^ v comp + The voltage loop gain with open current loop is: T v ( S ) = KFm F 1 ( S )A v ( S ) (EQ. 25) He(S) -Av(S) FIGURE 32. SMALL SIGNAL MODEL OF SYNCHRONOUS BUCK REGULATOR The Voltage loop gain with current loop closed is given by: Tv ( S ) L v ( S ) = ----------------------1 + Ti ( S ) V FB K = ---------- , V (EQ. 26) PWM COMPARATOR GAIN FM: The PWM comparator gain Fm for peak current mode control is given by: 1 d F m = ---------------- = ------------------------------ ( S e + S n )T s v comp (EQ. 20) FB is the feedback voltage of the voltage Where Vo error amplifier. If Ti(S)>>1, then the above equation can be simplified as follows: Where Se is the slew rate of the slope compensation and Sn is given by V in - V o S n = R t --------------------L (EQ. 21) S 1 + ---------- esr A v ( S ) V FB R o + R L 1 L v ( S ) = ---------- -------------------- --------------------- ---------------- , p -------------Vo S H (S) RT Ro Co 1 + ------ e p (EQ. 27) where RT is trans-resistance, and is the product of the current sensing resistance and gain of the current amplifier in current loop. CURRENT SAMPLING TRANSFER FUNCTION He(S): In current loop, the current signal is sampled every switching cycle. It has the following transfer function: S S H e ( S ) = ------ + -------------- + 1 2 Q nn n 2 From the above equation, it is shown that the system is a single order system, which has a single pole located at p before the half switching frequency. Therefore, a simple type II compensator can be easily used to stabilize the system. (EQ. 22) where Qn and n are given by 2 Q n = - -- , = n = f s 22 FN9116.0 April 18, 2005 ISL6232 Vo R2 C3 V FB V REF GM + R1 C2 C1 V COMP Example: Vin = 12V, Vo = 5V, Io = 5A, fs = 300kHz, Co = 180F/12m, L = 6.8H, gm = 100S, RT = 0.128 (Rcs = 8m, Ac = 16), VFB = 0.8V, Se = 1.5x105V/s, Sn = 1.318x105V/s, fc = 45kHz, then compensator resistance R1 = 400k. Put the compensator zero at 1.5kHz (~1.5x CoRo), and put the compensator pole at esr zero which is 49kHz. The compensator capacitors are: C1 = 270pF, C2 = 10pF (There is approximately 8pF parasitic capacitance from VCOMP to GND; Therefore, C2 optional). Figure 34 shows the simulated voltage loop gain. It is shown that it has 30kHz loop bandwidth with 85 phase margin and 20dB gain margin. FIGURE 33. TYPE II COMPENSATOR Figure 33 shows the type II compensator and its transfer function is expressed as follows: S S 1 + ------------ 1 + ------------ cz2 gm cz1 v comp S) = ---------------- = -------------------- -------------------------------------------------------- C1 + C2 S v FB S 1 + --------- cp (EQ. 28) GAIN (dB) 60 40 20 0 -20 -40 -60 100 VLOOP where C1 + C2 1 1 cz1 = -------------- , cz2 = -------------- , cp = ---------------------R1 C1 R1 C1 C2 R2 C3 1*103 1*104 1*105 1*106 Compensator design goal: High DC gain Loop bandwidth fc: -- to ------ f s 4 10 1 1 110 85 60 35 10 -15 -40 100 1*103 FREQUENCY (Hz) Gain margin: >10dB PHASE(o) VLOOP Phase margin: 40 The compensator design procedure is as follows: 1 -------------Put compensator zero cz1 = ( 1to3 ) R C oo Put one compensator pole at zero frequency to achieve high DC gain, and put another compensator pole at either esr zero frequency or half switching frequency, whichever is lower. CZ2 is an internal zero due to 8pF and 600k. The loop gain Tv(S) at cross over frequency of fc has unity gain. Therefore, the compensator resistance R1 is determined by 2f c V o C o R T R 1 = ----------------------------------g m V FB (EQ. 29) 1*104 1*105 1*106 FIGURE 34. SIMULATED LOOP GAIN 12V Auxiliary Supply A flyback transformer, or coupled inductor can be substituted for the inductor in 5V or 3.3V supply to generate an 12V auxiliary output as shown in Figure 35, which can be used to drive N-channel MOSFETs. The ISL6232 is particularly well suited for such applications because it can be configured in ultrasonic or forced PWM mode to ensure good load regulation when the main supplies are in light load where gm is the trans-conductance of the voltage error amplifier. Compensator capacitor C1 is then given by 1 1 C 1 = ----------------- ,C 2 = -----------------------R 1 cz 2R 1 f esr (EQ. 30) 23 FN9116.0 April 18, 2005 ISL6232 conditions. An additional post-regulation circuit can be used to improve load regulation if necessary. The power requirements of the auxiliary supply must be considered in the design of the main output. The flyback transformer must be designed to deliver the required current in both the primary and the secondary outputs with the proper turns ratio and inductance. The overcurrent limit threshold may also be adjusted accordingly. Power from the main and secondary outputs is combined to get an equivalent current referred to the main output, which is given by the following equation. P main + P auxiliary I total = ------------------------------------------------V OUT (EQ. 31) PCB Layout Guidelines Careful PC board layout is critical to achieve minimal switching losses and clean, stable operation. This is especially true when multiple converters are on the same PC circuit board, where one circuit can affect the other due to the noise coupling through the power ground. The switching power stages require particular attention. Mount all of the power components on the top-side of the board with their ground terminals flush against one another, if possible. Use the following guidelines for good PC board layout: * Isolate the power components from the sensitive analog components. Use a separate power plane ground and signal power ground if possible. * Use a star ground connection on the power plane to minimize the cross-talk between OUT3 and OUT5. * Keep the high-current paths short, especially at the ground terminals. This practice is essential for stable, jitter-free operation. * Keep the power traces and load connections short. This practice is essential for high efficiency. Using thick copper PC boards (2oz vs. 1oz) can enhance full-load efficiency by 1% or more. Correctly routing PC board traces must be approached in terms of fractions of centimeters, where a single milliohm of excess trace resistance causes a measurable efficiency loss. * When trade-offs in trace lengths must be made, it is preferable to allow the inductor-charging path to be made longer than the discharge path. For example, it is better to allow some extra distance between the input capacitors and the high-side MOSFET than to allow distance between the inductor and the synchronous rectifier or between the inductor and the output filter capacitor, because the synchronous rectifier conduction time is usually longer than that of high-side MOSFET. * Ensure that the OUT connection to the output capacitors is short and direct. This reduces the voltage spike or dip due to the trace resistance between OUT and output capacitors. * Route high-speed switching nodes (BOOT, UGATE, PHASE, and LGATE) away from sensitive analog areas (REF, COMP, FB, and CS). Use PGND3 and PGND5 as an EMI shield to keep radiated switching noise away from the ICs feedback divider and analog bypass capacitors. * Keep the FB traces as short as possible for good radiated immunity design. where Pmain and Pauxiliary are the main power and auxiliary power, respectively. For the circuit in Figure 35, the turns ratio N of the flyback is determined by V SEC + V F - V OUT N = --------------------------------------------------V OUT + V RECT (EQ. 32) where VSEC is the minimum required rectified secondary voltage, VF is the forward voltage drop across the secondary rectifier, and VRECT is the on-state voltage drop across the synchronous rectifier MOSFET. The secondary rectifier in the flyback must withstand flyback voltages, which is given by the following formula V REV = V SEC + N * ( V IN - V OUT ) (EQ. 33) The secondary rectifier's reverse breakdown voltage rating must also accommodate any ringings due to leakage inductance. This voltage ringings can be minimized by adding a snubber circuit across the secondary rectifier. Its current rating should be at least twice the DC load current on the auxiliary output. The optional linear post regulator must be selected to deliver the required load current, and it should be configured to run close to dropout to minimize power dissipation. LDO Optional ISL6232 D1 BOOT5 UGATE5 PHASE5 LGATE5 T: Delta Electronics STQ125-6822 Q1 R 1:N 1: N H T: L1- 6.8 y H N = 2.2 D2 OUT5 4.7F 4.7 12V/20mA 12V Q2 FIGURE 35. FLYBACK SECONDARY OUTPUT 24 FN9116.0 April 18, 2005 ISL6232 Quarter Size Outline Plastic Packages (QSOP) N INDEX AREA H E -B1 2 3 SEATING PLANE -AD -CA 0.25 0.010 h x 45o L GAUGE PLANE 0.25(0.010) M BM M28.15 28 LEAD QUARTER SIZE OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 B C D E e H MIN 0.053 0.004 0.008 0.007 0.386 0.150 MAX 0.069 0.010 0.061 0.012 0.010 0.394 0.157 MILLIMETERS MIN 1.35 0.10 0.20 0.18 9.81 3.81 MAX 1.75 0.25 1.54 0.30 0.25 10.00 3.98 NOTES 9 3 4 5 6 7 8o Rev. 0 2/95 0.025 BSC 0.228 0.0099 0.016 28 0o 8o 0.244 0.0196 0.050 0.635 BSC 5.80 0.26 0.41 28 0o 6.19 0.49 1.27 A1 0.10(0.004) A2 C e B 0.17(0.007) M C AM BS h L N NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "B" does not include dambar protrusion. Allowable dambar protrusion shall be 0.10mm (0.004 inch) total in excess of "B" dimension at maximum material condition. 10. Controlling dimension: INCHES. Converted millimeter dimensions are not necessarily exact. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 25 FN9116.0 April 18, 2005 |
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